With the growing need for higher densities in integrated circuits, the STI (shallow trench isolation) process has gradually replaced the LOCOS (local oxidation of silicon) process. The STI process begins with the formation of shallow trenches in the surface of the silicon wafer following which these trenches are over-filled with a suitable dielectric material, typically silicon oxide, the excess being then removed by means of CMP (chemical mechanical polishing). In principle, the advancing etch front during CMP should be flat and independent of the initial surface contours, hence its popularity for planarization. In practice, however, the advancing front is not always as flat as would be desired, being influenced as much by the nature of the materials being etched as by the initial surface contour. For example, the CMP removal rate of an oxide layer will be lower where it is underlaid by another layer of oxide and higher where it is underlaid by a layer of metal.
As a consequence, the amount of material that is removed after CMP, as well as the time needed to remove it, will vary from one wafer to the next if the underlying metal patterns (which in turn depend on the particular technology and circuits that are being implemented) are different.
Clearly, it is possible to determine the optimum polishing time for any given class of wafers by purely empirical means such as conducting a test run involving several different polishing times each time a new wafer design is to be implemented. Pilot runs of this type are, however, very time-consuming (typically 8-10 hours), rendering this approach expensive, particularly if the technology being calibrated is not to be manufactured in large quantities.
There have, therefore, been a number of suggested approaches as to how to determine the optimum polishing time (i.e. the optimum amount of dielectric to be removed) without the need to go through a pilot run.
For example, Li et al. (U.S. Pat. No. 5,659,492) measure the times to first break through the film being polished. Then the time to completely remove the film is measured and the two numbers are added to give the total required polishing time.
Cote (U.S. Pat. No. 5,234,868) determines an end point for CMP by using an underlayer of different visual appearance from the layer that is being removed.
Schoenborn et al. (U.S. Pat. No. 5,298,110) first measure removal rates inside and outside the trenches to determine their relative polishing rates. This information is used to predict optimum polishing times for future wafers.
Sahota et al. (U.S. Pat. No. 5,665,199) first polish at least two test wafers then measure the amount removed in four selected locations so as to characterize the extent of polish rate variation across the wafer. They then use this data to determine the optimum polishing time.
Hoffman et al. (U.S. Pat. No. 5,552,996) divide the wafer surface up into a number of sub-regions. Optimum polishing time is determined for each sub-region and this data is then used to compute an optimum polishing time for a full wafer.
All of these approaches, while possibly representing an improvement over a full blown pilot study, are still very time-consuming. The present invention presents an approach that involves two hours or less to implement but that nevertheless provides a highly reliable guide as to how much material is to be removed in any particular case.